A central processing unit (CPU) is the computing and control hardware element of a computer-based system. In a personal computer (PC), for example, the CPU is usually an integrated part of a single, extremely powerful microprocessor. An operating system (OS) is the software responsible for allocating system resources including memory, processor time, disk space, and peripheral devices such as printers, modems, and monitors. All application programs use the OS and CPU to gain access to these resources as necessary. The OS is the first program loaded into the computer as it boots up, and it remains in memory throughout the computing session.
Advanced CPU's and embedded processors are achieving higher performance as time goes on. However, memory subsystems are requiring lower latency and more bandwidth to sustain performance. For example, dynamic random access memory (DRAM), including that configured into dual in-line memory modules (DIMM), is getting faster in clock speed, wider in data and/or address bus size, and larger in capacity. As a result, DRAM/DIMM memory is consuming more power and generating more heat. The wider bus effectively increases the memory subsystem power consumption linearly, whether it is for embedded appliances, Desktop/Notebook PC's, or high-density server applications. It is possible that a single DRAM and/or DIMM component can be the target of nearly all bus activity and thus consume much more power than other memory components on the same channel.
In many computer systems, the power consumption of DRAM/DIMM memory is insignificant compared to other system components such as hard disks, high-performance microprocessors, active matrix displays, monitors, etc. However, in other computer systems, such as for example in the newly emerging and evolving class of mobile devices known as “handhelds” or “PDAs” (“personal digital assistants”), the power consumption of the memory is significant as compared to other components in the computer system. Also, servers can utilize large arrays of memory with hundreds or thousands of devices where the memory subsystem becomes the dominant consumer of power in the system. As a result of these and other factors, power consumption of memory subsystems has become more of an issue, so there is a strong need to reduce memory power consumption.
Memory devices with power management features are becoming available to address this need. For example, DRAM/DIMM components are available that support various different reduced power modes. However, power savings come at the cost of performance. Typically, a greater penalty in access speed is imposed at each increasing degree of power savings. Thus, decisions regarding whether to invoke power-saving features in memory components should be made intelligently. Typically, it is desired to initiate a low power mode in a particular memory device only when that memory device is not currently in use and is not anticipated to be in use in the near future.
It is difficult, however, to anticipate the future need for accessing any particular region of memory. Furthermore, modern operating systems typically allocate memory without regard to memory device boundaries, making it difficult to find a single memory device that can appropriately be set to a reduced power mode without significantly impacting overall system performance. More specifically, typical memory allocation schemes often result in a highly fragmented memory space, with allocated pages of memory spread more or less randomly across the available range of physical memory. Because allocated memory is normally spread across all of the available devices, none of the devices can be put into a reduced power mode without seriously impacting memory performance.
Certain teachings of the prior art provide a means for performing adaptive memory power management in a system employing a CPU along with a memory subsystem involving DRAM and/or DIMM components. In particular, certain embodiments provide for controlling the periodicity of operation (i.e. “throttling”) of the CPU and/or memory by monitoring actual processes of the CPU and memory subsystem from one time segment to another, and determining which portions of the memory subsystem to power down for at least the next time segment based on whether the CPU and the monitored memory processes are to be active during that time segment. This has the advantage of reducing memory component power and cooling at the system level but can only protect an individual component with an unacceptable reduction in system performance.
Other teachings of the prior art describe memory power conservation using specific techniques for minimizing the number of actual DRAM/DIMM devices being used in a system at any particular time. In one such prior art embodiment, the memory controller can identify highly used portions of the logical and/or virtual memory address space by monitoring memory instructions in order to keep track of which addresses are specified most frequently and/or most recently in the memory instructions. In this way, the memory controller is configured to periodically re-map the logical and/or virtual address space to physical memory in order to reduce the number of physical memory devices accessed by the highly-used portions of that address space. Specifically, the address translation entries are periodically re-calculated so that the most frequently and/or recently used logical and/or virtual memory addresses map to physical memory that is located in the fewest possible number of physical memory devices or ranks. Depending on system constraints which set the maximum power consumption of the memory system, the most frequently and/or recently used addresses can be mapped to devices that are the most active and thus consume more power and have the highest performance. Conversely, addresses that are used less frequently and/or less recently can be mapped to devices that are less active and thus consume less power and have lower performance. In conjunction with this re-mapping process, memory content is copied or moved as appropriate so that all logical and/or virtual memory addresses will continue to reference the same data even though the data might now be in a different physical location.
However, these types of prior art systems suffer from the disadvantages inherent with such “throttling” and reduced power modes, which typically affect an entire DRAM/DIMM memory device or multiple ranks within a device (or in certain cases even more than one device) rather than impacting individual cells or rows within such memory devices. In these cases, system performance may be compromised if a memory instruction is not executed correctly due to “throttling” or reduced power operation when memory access is requested by the CPU.
These problems are solved by the apparatus and methods of the present invention, which identify and track memory usage to minimize power consumption in a way that lessens the detrimental effects of “throttling” or reduced power modes, by redistributing memory allocation to portions of DRAM/DIMM devices that are underutilized in order to balance memory usage more evenly among active devices.
Further, because the prior art implements memory “throttling” and/or remapping the memory address space in a way that reduces the total number of physical memory devices being utilized in order to lessen power consumption, these prior art systems teach away from the present invention by requiring consolidation of memory use, rather than even redistribution of memory allocation to accomplish power conservation while also minimizing the need for “throttling” or reduced power operation.